General CMOS silicon gate technology has been scaled rapidly from the 1.0 μm generation (VDD=5.0 V) to the 0.13 μm generation (VDD=1.5 V) over a period of little over a decade. However, the progress of scaling Flash/NV programming voltage and power has been limited. Additionally, the Flash/NV devices have a limited endurance. That is, these devices are capable of performing a limited number of write/erase cycles that prevent their use in a number of applications. The progress of extending the endurance of Flash/NV devices also has been limited.
Most NV devices have a floating gate and use a power hungry channel hot electron write process and a tunnel erase process through the tunnel oxide. The tunnel erase process requires both a high programming voltage and a programming field that approaches the breakdown of the oxide. Thus, conventional Flash/NV devices require attributes of high voltage technology and circuitry in an environment of scaled low voltage CMOS technology. As such, the integration of NV devices with general high performance logic technology and DRAM technology is complicated. Additionally, the endurance of these NV devices is limited to about 10E5-10E6 cycles. Therefore, providing embedded Flash/EPROM in a general random logic or DRAM environment to achieve enriched functions requires complex circuitry and many additional masks, resulting in a relatively limited yield and high cost.
Two phase insulating materials, referred to as silicon-rich insulators (SRI), are known. SRI includes controlled and fine dispersions of crystalline silicon in a background of stoichiometric insulator such as SiO2 (referred to as silicon-rich oxide or SRO), or Si3N4 (referred to as silicon-rich nitride or SRN). A unique set of insulators with a controlled and wide range of electrical properties can be formed by controlling the amount, distribution and size of silicon crystals.
SRI materials are capable of possessing charge trapping and charge injecting properties. “Charge-centered” SRI has refractive index in a range that provides the material with the property for trapping electrons or holes at the silicon centers due to the creation of quantum potential wells. “Injector” SRI has a refractive index in a range that provides the material with silicon centers that are within tunneling distance of each other such that charge can readily communicate between the charge centers. Injector SRI is characterized by high conductivity and behaves like semi-metal. The apparent high frequency dielectric constant of this material is greater than that of silicon. When superimposed on top of a dielectric, charge injected into this material from a metal plate is uniformly distributed to the silicon centers, which in turn injects charges uniformly into the insulator when biased. Thus, the injector SRI reduces local field fluctuations due to defects. At the same time, a large number of silicon injector centers at the insulator interface provides a geometrical pattern that enhances the tunneling, and thus the charge transfer or conduction, at significantly reduced average fields. This material has been termed an “injector” because of this enhanced tunneling.
Charge-centered or trapping SRI is a charge storing medium that includes charge-centered SRO characterized by a refractive index in the approximate range of 1.5 to 1.6, and further includes charge-centered SRN characterized by a refractive index in the approximate range from 2.1 to 2.2. Injector SRI is a charge injector medium that includes injector SRO characterized by a refractive index that is approximately 1.85 and greater, and further includes injector SRN characterized by a refractive index that is approximately 2.5 and greater. It was observed that the SRN class of materials was significantly more stable at high temperature compared to SRO in terms of interdiffusion and growth of silicon centers during high temperature processing as well as in terms of providing a reproducible interface between silicon and SRI and/or SiO2 and SRI.
It has been proposed to use charge centered and injector SRI material in a variety of NV FET structures and associated Flash, PROM, EPROM, EEPROM, antifuse cells and arrays. In one of these proposed embodiments, the gate insulator stack includes a tunnel oxide, a thin layer of charge-centered SRN to trap charges and thereby act like a “floating plate,” an overlayer of thicker CVD oxide, and a layer of injector SRN. The top CVD oxide is designed to prevent charge loss at the operating field and to be optimized for the appropriate programming voltage. The equivalent oxide thickness (tox) of the gate insulator stack is primarily dependent on the tunnel oxide and the barrier CVD oxide thickness. The stack is scalable with respect to the programming voltage because the required programming field is reduced to 6-7E6 V/cm due to the injector-induced enhanced tunneling compared to 10-11E6 V/cm for a conventional NV/FET structure. Additionally, the programming gate voltage is directly coupled into the charge-centered layer to provide 100% coupling efficiency compared to the typical floating gate structures where capacitor divider effects and the cell geometry determine the coupling efficiency. The coupling efficiency for a floating gate structure is typically around 50%-70%. These proposed devices were shown to exhibit many orders of magnitude greater retention because of the reduced programming field. These devices are significantly more power efficient as they are written to and erased by direct tunneling, rather than by channel hot electron injection. However, the write/erase fields were still too high, and both the endurance and power reductions were still too limited.
Silicon “quantum dots” of 3 nm to 10 nm diameter have been fabricated in a controlled manner by either Low Pressure Chemical Vapor Deposition (LPCVD) followed by oxidation or by gas phase pyrolysis of silane to create nano crystal silicon aerosol. It has been proposed to either place these silicon nano crystals on top of the tunnel oxide or embed them into the gate insulator oxide. These nano crystals behave as charge centers similar to the charge-centered SRI layer described above. NV FET gate stacks were formed with the silicon quantum dots by adding a thicker oxide overlayer. While somewhat reduced voltage write/erase and up to 10E6 endurance were demonstrated, the write/erase fields were still too high, and both the endurance and the power reductions were still too limited.
Therefore, there is a need in the art to provide Flash/NV technology that overcomes these problems by being capable of using scalable programmable voltages and power, by being easily integratable with general scaled logic technology while minimizing the overhead associated with Flash/NV technology features, by extending endurance, and by providing faster write-erase cycles without impacting retention and reliability.